1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a transistor with a borderless contact.
2. Description of Related Art
As device dimension is greatly reduced, a metal-oxide semiconductor (MOS) transistor dimension is also accordingly reduced. The highly reduced MOS transistor therefore has insufficient junction area for a formation of a landed contact. A strategy of unlanded contact is then widely taken in the current semiconductor fabrication. The unlanded contact is also called a borderless contact, which allows a contact to be formed without fully landing on the junction area of the MOS transistor.
FIGS. 1A-1E are cross-sectional views of a portion of a substrate, schematically illustrating a conventional fabrication process for forming a transistor with a borderless contact. In FIG. 1A, a pad oxide layer 20 and a silicon nitride layer 30 are sequentially formed over a semiconductor substrate 10. A trench 39 in the substrate 10 is formed by etching the substrate 10. An active area 35 between each trench 39 is simultaneously formed. A shallow trench isolation (STI) structure 40 is formed by filling the trench 39 with insulating material.
In FIG. 1B, the silicon nitride layer 30 is removed. An ion implantation is performed to dope the substrate 10 on the active area 35 so as to form a well 50. In the well 50, the ion implantation process is continuously performed to form a threshold voltage doped region 60 and an anti-punch-through doped region 70 below the threshold voltage doped region 60.
In FIG. 1C, the pad oxide layer 20 is removed. A thermal oxidation process is performed to form a gate oxide layer 80 on the substrate 10. A doped polysilicon layer 90, a tungsten silicide layer 100, and a cap silicon nitride layer 110 are sequentially formed on the pad oxide layer 80 and are patterned to form a gate structure 115 shown in FIG. 1C.
In FIG. 1D, using the gate structure 115 as a mask, an interchangeable source/drain regions 120 is formed by ion implantation in the substrate 10 at each side of the gate structure 115. Two spacers 130 including silicon nitride are respectively formed on each sidewall of the gate structure 115.
In FIG. 1E, a dielectric layer 140 including silicon oxide is formed over the substrate 10. A contact opening 150 is formed to ideally expose the interchangeable source/drain region 120. Since an unlanded strategy is applied, the borderless contact opening 150 is formed. The borderless contact opening 150 also exposes a portion of the STI structure 40. The borderless contact opening 150 is filled with metallic material to form a contact plug 160, or called a contact 160, which is usually coupled to a bit line.
In this conventional fabrication process, it has several issues as follows:
1. Since the contact 160 in a kind of borderless contact, the contact opening 150 is not precisely formed on the interchangeable source/drain region 120. When an etching process is performed to form the contact opening 150, because the STI structure 40 is also made of silicon oxide, it is also etched during the formation of the contact opening 150. If the etching process is properly controlled, the etching process can easily over-etch the STI structure 40 with a greater depth than the junction depth of the interchangeable source/drain region 120 as shown in FIG. 1E. When the contact 160 is formed, it has an electrical coupling with the substrate 10, resulting in a short circuit of the MOS transistor.
2. The contact open 150 is formed by etching the dielectric layer 140 and the gate oxide layer 80 so that the aspect ratio, which is a ratio of depth to width in an opening, of the contact opening 150 is relatively large. This causes a poor step coverage capability to deposit the contact opening 150 with doped polysilicon.
3. The threshold voltage doped region 60 formed in the well 50 produces an extra series resistance to the interchangeable source/drain region 120. The anti-punch-through doped region 70 is close to the interchangeable source/drain region 120 so that a dopant density around the interchangeable source/drain region 120 is increased. This causes an extra junction capacitance of the interchangeable source/drain region 120.
4. Since the interchangeable source/drain region 120 is formed by ion implantation, a driving-in process is usually necessary to diffuse the implanted ions so as to obtain a uniform ion distribution. The driving-in process may also cause a lateral diffusion so that a short channel effect may easily occur. Moreover, since the ion implantation may also causes a certain degree of damage to the substrate 10, a junction leakage can also occur.